This invention relates to an output circuit for a semiconductor integrated circuit for use with a field-effect transistor (hereafter referred to as a MOST).
FIG. 1 shows a system in which the output terminals of two semiconductor integrated circuits are connected to conventional output circuits.
It is generally well known to connect terminals of a plurality of semiconductor integrated circuits, as shown, in common with one another and to use such common terminals as output terminals for such system.
In FIG. 1, numeral 10a designates the output circuit component for a first semiconductor integrated circuit A. At 1a and 2a are its output terminal and a terminal to which a power source (high level) voltage is applied. At 3a is a pull up MOST connected between the power source terminal and the output terminal 1a. At 4a is a pull down MOST connected between the output terminal 1a and ground. Numeral 5a is a terminal to which a signal OUT for controlling the MOST 3a is applied. At 6a is a terminal to which a signal OUT for controlling the MOST 4a is applied, in complementary relation with the signal OUT. A MOST 7a is connected between the terminal 5a and ground, and a MOST 8a is connected between the terminal 6a and ground. A terminal 9a receives a signal CS1 for controlling the MOSTs 7a, 8a.
Terminals lb-9b in an output circuit 10b for a second semiconductor integrated circuit B correspond to those at 1a-9a in the output circuit 10a for the first semiconductor integrated circuit. At reference numeral 11 is a common output terminal of the output circuits 10a, 10b for the two semiconductor integrated circuits.
Now, the operation of the circuit shown in FIG. 1 will be explained. For convenience of illustration, all of the MOSTs used in the circuit may be taken as n-channel MOSTs.
In the system shown in FIG. 1, in which the output terminals of a plurality of the semiconductor integrated circuits are connected in common with each other, the output state of either one of the selected semiconductor integrated circuits may be present at the output terminal whereas the output state of the other semiconductor integrated circuit is in a non-selected condition and is controlled so as to exert no influence upon the output terminal 11. To this end, MOSTs 7a, 8a and 7b, 8b are provided to render each of the semiconductor integrated circuits selected or non-selected. Chip select signals CS1 and CS2 are transmitted to the respective gates of the MOSTs. Now, for transmission of the output state of only the semiconductor integrated circuit 10a (FIG. 1) from the output terminal 1a thereof to the output terminal 11, the chip select signals CS1 and CS2 are respectively set at "0" and "1". Under such circumstances complementary signals are applied to the terminals 5a, 6a to transmit these signals to the gates of the MOSTs 3a, 4a, presenting a "1" or "0" to the output terminal 1a according to the level of these signals. For instance, if the signal OUT to the terminal 5a and the signal OUT to the terminal 6a are "1" and "0", respectively, a "1" is output to the output terminal 1a since the MOST 3a is turned on and the MOST 4a is non-conductive. On the other hand, the MOSTs 7b, 8b conduct as the chip select signal CS2 is set at "1" on the side of the semiconductor integrated circuit B; however, the MOSTs 3b and 4b do not conduct as the gates thereof are grounded, rendering the terminal lb floating. Accordingly, a signal transmitted to the terminals 5b, 6b is not present at the terminal 1b. If it is desired to transmit the output from the side of the semiconductor integrated circuit B, the chip select signals CS1 and CS2 are set at "1" and "0". According to the system designated as above, control is performed using the chip select signals CS so as to turn off the MOSTs of one output circuit when the other output circuit is actuated. If the other output MOSTs are enabled, interference is caused between the two outputs, causing deterioration of the "1", "0" levels at the terminal 11.
In a system of the class as aforementioned, the output MOSTs on the non-selected side are required to create a discontinuity. On the other hand, the output MOSTs 3, 4 are required to have short channel lengths to increase the switching speed thereof. However, a reduction in the channel lengths of the MOSTs 3, 4 lowers the threshold value of the MOSTs more than required due to the "short channel effect".
In this instance, the MOSTs do not create a discontinuity to the full extent, i.e., the channel is not turned off completely, even if the terminals 5, 6 are grounded so as to maintain the gate voltages of the output MOSTs 3, 4 at the ground level. This phenomenon has been previously discussed by Nishizawa et al. in their article. "A Limitation of Channel Length in Dynamic Memories", Journal of Solid-State Circuits, Vol. SC-15, No. 4, August 1980. The resistance of the MOSTs often amounts to a value of several M.OMEGA.--several hundred M.OMEGA..
If 100 output circuits in a non-selected condition are connected to common output terminals, the common resistance amounts to a value of several tens of k.OMEGA.--several k.OMEGA. to thus involve an adverse effect upon the output level derived from the output circuit in a selected condition.